Manufacturing & Reliability Data for Lead Free Flip Chip Solder Bumping based on IBM’s C4NP process

High-end microelectronic packaging is increasingly moving from wire bonds to solder bumps as the method of interconnection. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. Flip chip in Package (FCiP) requires many small bumps on tight pitch whereas Wafer Level Chip Scale Packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. All these established bumping technologies have important limitations for fine pitch, especially with lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the Europe-an Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry. C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by SUSS MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into prefabricated and reusable glass templates (molds). The mold is inspected prior to solder transfer to the wafer to ensure high final yields. Mold and wafer are brought into close proxi-mity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper provides a summary of the most recent manufacturing and reliability results of C4NP bumped, 300mm wafer, high-end logic device packaging. This includes extensive reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. It discusses the relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process. The paper also reviews the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques.